TXS=ENDPOINT_OK_THIS_BI, RXE=ENDPOINT_DISABLED_, RXI=DISABLED, TXE=ENDPOINT_DISABLED_, RXT=CONTROL, RXS=ENDPOINT_OK_THIS_BI, TXI=ENABLED, TXT1_0=CONTROL
Endpoint control
| RXS | Rx endpoint stall 0 (ENDPOINT_OK_THIS_BI): Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. 1 (ENDPOINT_STALLED_SOF): Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. |
| RESERVED | Reserved |
| RXT | Endpoint type 0 (CONTROL): Control 1 (ISOCHRONOUS): Isochronous 2 (BULK): Bulk 3 (RESERVED): Reserved |
| RESERVED | Reserved |
| RXI | Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID. 0 (DISABLED): Disabled 1 (ENABLED): Enabled |
| RXR | Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device. |
| RXE | Rx endpoint enable An endpoint should be enabled only after it has been configured. 0 (ENDPOINT_DISABLED_): Endpoint disabled. 1 (ENDPOINT_ENABLED_): Endpoint enabled. |
| RESERVED | reserved |
| TXS | Tx endpoint stall 0 (ENDPOINT_OK_THIS_BI): Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. 1 (ENDPOINT_STALLED_SOF): Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. |
| RESERVED | Reserved |
| TXT1_0 | Tx endpoint type 0 (CONTROL): Control 1 (ISOCHRONOUS): Isochronous 2 (BULK): Bulk 3 (INTERRUPT): Interrupt |
| RESERVED | reserved |
| TXI | Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID. 0 (ENABLED): Enabled 1 (DISABLED): Disabled |
| TXR | Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device. |
| TXE | Tx endpoint enable An endpoint should be enabled only after it has been configured 0 (ENDPOINT_DISABLED_): Endpoint disabled. 1 (ENDPOINT_ENABLED_): Endpoint enabled. |
| RESERVED | reserved |